1. Field of the Invention
The present invention relates to an electronic device, an electronic device sealing method and an electronic device connecting method and, more particularly, an electronic device such as a semiconductor device, a wiring substrate, etc. that have external terminals, an electronic device sealing method and an electronic device connecting method.
2. Description of the Prior Art
With the progress of the miniaturization, the high function, and the high integration of the semiconductor device, the number of input/output terminals tends to increase. Also, in the semiconductor device, there is the request to reduce a size of the package that covers the semiconductor device chip. Under such circumstance, the technology of the semiconductor package that is suitable for the high-density packaging of the semiconductor device is being developed.
In the semiconductor device, the structure for packaging the external terminals on one surface is developed with regard to the alignment margin of the external terminals and the reduction of the packaging burden. There are various types such as BGA (Ball Grid Array), LGA (Land Grid Array), PGA (Pin Grid Array), etc.
The external terminals of such semiconductor device are connected to the wiring or the terminals on the substrate via the solder.
For example, as shown in FIG. 1A, a semiconductor device 103 having uppermost wiring patterns 102, to which a solder 101 is jointed, as the external terminals and a mother board 105 having terminals 104 on its uppermost surface are prepared. Then, the solders 101 on the semiconductor device 103 are superposed on the terminals 104 on the mother board 105. Then, as shown in FIG. 1B, the terminals 104 and the wiring patterns 102 are jointed by heating/melting the solders 101. Accordingly, the semiconductor device 103 and the mother board 105 are electrically and mechanically connected.
By the way, as shown in FIG. 1B, if the semiconductor device 103 and the mother board 105 are connected via the solders 101, the solders 101 are brought into the state that they are exposed to the outside. Therefore, depending upon to the material of the solder or the material of the external terminals, there is the fear that the solders 101 are reacted with the gas in the outside air and then are degraded.
Also, if the size of the semiconductor circuit device is reduced up to the chip size, the capability of relaxing the thermal stress becomes low rather than the prior art and thus the stress tends to concentrate to the packaging portion of the external terminals. As a result, there is the fear that the cohesion destruction is generated in the jointed portions of the external terminals to which the stress is concentrated. Also, if the external terminals are the pin-type one, there is the possibility that the external terminals are deformed or folded due to the stress concentration.